Expert-Led Training for Design Assurance and Verification Teams

AeroDAS training is delivered by an expert team with practical experience in aerospace engineering, FPGA development, digital verification, systems engineering, and certification-oriented hardware programs. Programs are designed to help participants connect standards and methods with the engineering decisions, work products, and evidence expected in real projects.

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A whiteboard map of the DO-254 life cycle, linking planning, requirements and traceability, HDL, FPGA and ASIC design, verification and validation, reviews, configuration management, problem reporting, safety, and certification. — The DO-254 life cycle our programs work through, from planning to certification liaison.

Technical Webinar Speakers

AeroDAS provides expert speakers for technical webinars, conferences, professional communities, and internal corporate events.

Sessions can cover DO-254, AMC 20-152A, FPGA design assurance, requirements traceability, verification strategy, SystemVerilog/UVM, simulation-to-HIL workflows, and certification readiness.

Webinars may be delivered as standalone technical sessions, moderated discussions, panel contributions, or customized events for engineering organizations.

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DO-254 and AMC 20-152A Training

Design assurance for airborne electronic hardware brings together requirements, engineering activities, and evidence supporting compliance.

AeroDAS training covers a learning path from DO-254 / ED-80 fundamentals to practical application and advanced topics under AMC 20-152A. Choose the course that matches your experience and project responsibilities to strengthen your understanding of hardware development, verification, and design assurance.

All courses are available online or on-site at your organisation.

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D254-AW · Foundation

DO-254 Awareness

An introduction to design assurance for airborne electronic hardware.

Focus: Fundamental concepts and project responsibilities
Intended audience: Professionals new to DO-254 or seeking a high-level understanding

2 days · Online or on-site

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D254-CP · Practitioner

DO-254 Comprehensive Practitioner

Build a comprehensive understanding of the DO-254 lifecycle and supporting processes.

Focus: Hardware lifecycle, supporting processes, and compliance planning
Intended audience: Professionals involved in development, verification, and assurance

3 days · Online or on-site

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D254-AP · Practitioner

DO-254 Applied Practitioner

Apply DO-254 knowledge through practical engineering exercises.

Focus: Practical application through worked examples
Intended audience: Practitioners seeking to apply DO-254 knowledge to engineering activities

5 days · Online or on-site

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AMC-ADV · Advanced

AMC 20-152A Advanced Training

Understand AMC 20-152A objectives and assess their applicability to your project.

Focus: Additional objectives and applicability
Intended audience: Engineers and technical leads with an established DO-254 foundation

2 days · Online or on-site

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AMC-APP · Advanced

AMC 20-152A Applied Advanced

Apply advanced guidance to practical project scenarios.

Focus: Scenario-based compliance activities
Intended audience: Teams applying AMC 20-152A objectives to project decisions

3 days · Online or on-site

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Verification Engineering Programs

Basic SystemVerilog / UVM Training

A practical introduction to SystemVerilog and the Universal Verification Methodology for engineers moving toward reusable, coverage-driven verification. Participants develop the core concepts needed to understand testbench architecture, transactions, sequences, drivers, monitors, agents, scoreboards, reference models, functional coverage, and test organization.

Typical learning outcomes

Understand the role of SystemVerilog in modern verification environments.
Explain the structure and responsibilities of common UVM components.
Create and reuse transaction-level stimulus through sequences.
Connect monitoring, prediction, checking, and coverage into a coherent verification flow.
Read, debug, and extend a basic UVM testbench.

UVM to HIL Training Platform

This practical four-day course demonstrates how to reuse UVM test intent between Questa RTL simulation and an AMD Kria KV260 hardware-in-the-loop target.

Format: Four-day course

Typical learning outcomes

Separate verification intent from backend-specific transport.
Reuse UVM stimulus, checking, and coverage across simulation and HIL execution.
Understand a mixed-language VHDL/SystemVerilog Questa workflow.
Connect SystemVerilog to a C++ runtime through a small DPI-C boundary.
Evaluate architectural tradeoffs when moving verification intent toward an FPGA-based HIL target.

The synthesizable device under test is written in VHDL-2008. Interfaces, UVM components, tests, and transport classes are written in SystemVerilog, making the simulation flow a deliberate Questa mixed-language example.

Central principle

A test describes what to verify. A transport describes where and how the DUT is reached.

The same packet_item, sequences, reference model, scoreboard, coverage model, and tests are reused with both backends. sim_transport drives SystemVerilog interfaces. hil_transport calls a compact DPI-C API and a C++ runtime.

AeroDAS engineering principle

“You cannot control what you cannot identify, and you cannot assure what you cannot control.”

AeroDAS training certificates confirm attendance, completion, or assessment results, depending on the selected program. They do not constitute an official regulatory certification or authority approval.